Formal Verification Engineer / Formal Verification Engineeress

Position Available: Formal Verification Engineer

Full-time position available immediately or by agreement.

Challenges drive us, and innovation is our calling. At Kandou, we are a team of passionate professionals making a significant impact in the semiconductor industry. As an innovative leader in high-speed and energy-efficient chip-to-chip link solutions, we are dedicated to evolving to meet the demands of both today's and tomorrow's customers. If you thrive in a high-tech scale-up environment and are motivated by pushing limits and challenging the status quo, we have an exciting opportunity for you.

Location

This position can be based in:

• Lausanne, Switzerland
• UK (Reading/Northampton)
• Germany (Dortmund)
• Denmark

Key Responsibilities

• Develop formal verification methodologies and best practices.
• Participate in RTL design reviews.
• Prepare design verification plans based on design specifications.
• Document results and coverage metrics for formal sign-off.
• Plan and schedule assigned projects for timely completion.
• Maintain the design verification environment and track & close design bugs.

Skills

• Excellent communication skills with a rigorous analytical mindset and a strong team spirit.
• Proficient in scripting techniques (Python, Perl, or TCL for automation), regression setup, and management.
• Deep understanding of formal verification technologies.
• Strong knowledge of metrics-driven verification, including test planning and coverage closure.
• Proficiency in temporal logic assertion-based languages such as SVA or PSL.
• Familiarity with traditional simulation-based verification methodologies is a plus.
• Exceptional analytical, problem-solving, and debugging skills.
• Strong understanding of instruction-set architectures, interrupt handling, and bus architectures.
• Knowledge of Cadence JasperGold and VManager is preferable.

Experience

• 5+ years of experience in the semiconductor industry.
• Proven track record in verifying complex designs (preferably in high-volume applications) - FPGA or ASIC.
• Adept at balancing quality and schedule trade-offs.
• Collaborating with RTL design engineers to develop formal micro-architecture specifications.
• Familiarity with SerDes and high-level protocols (e.g., PCIe, USB, DP) would be advantageous.
• Delivered reusable and optimized formal models and verification codebases to enhance project efficiency.

Education

• Bachelor of Engineering in Electronics and Electrical Engineering (equivalent or higher).

If this is the role you have been searching for and you wish to be part of a growing company with an exciting future, we would be thrilled to hear from you. Apply online using the form below. Please note, only applications matching the job profile will be considered.

Together We Kandou It!

Visit us at www.kandou.ai and Kandou on LinkedIn.