DFT Lead / DFT Leadess

Full-Time DFT Lead Position in Lausanne, Switzerland

At Kandou, we are driven by challenges and inspired by innovation. As a team of passionate professionals, we are making a significant mark in the semiconductor industry. As an innovative leader in high-speed and energy-efficient chip-to-chip link solutions, we are dedicated to meeting not only the demands of today's customers but also those of tomorrow. If you thrive in a high-tech scale-up environment and are motivated to push your limits and challenge the status quo, we have an opportunity for you.

Job Overview

We are actively seeking a resourceful DFT Lead to join our team based in Lausanne, Switzerland.

Key Responsibilities

• Lead DFT activities for the next generation of products.
• Drive the DFT architectures, methodologies, and tool flows for complex multi-million gate designs, including Analog/high-bandwidth SerDes, DDR, and PCIe designs.
• Collaborate closely with the Physical Implementation team to define timing constraints in test modes and assist in achieving successful tapeouts.
• Possess a solid understanding of ATE and be skilled in debugging issues during probe and final test bring-up, guiding the test engineering team towards successful silicon bring-up and test program development.
• Define test plans through close collaboration with teams and steer the development of functional/structural tests for final/wafer test programs.
• Work with teams to implement device qualification solutions for HTOL.
• Drive lab bench silicon debugging to understand ATE bring-up challenges.

Required Skills

• Excellent communication skills and a strong team player with a proactive attitude.
• Able to mentor team members effectively.
• Exceptional debugging skills.
• Proficient in scripting for automation development.

Qualifications

• 12+ years of DFT experience, encompassing architecture specification, implementation, test pattern development, and simulation.
• Proven track record in delivering DFT solutions for complex designs.
• Experience with IJTAG methodologies.
• Familiarity with hierarchical MBIST insertion, hierarchical scan insertion, and scan compression methodologies.
• Knowledge in ATPG pattern generation across various fault models, fault coverage analysis, and achieving high coverage metrics.
• Strong debugging capability in simulating patterns with timing.
• Experience in defining test mode constraints and analyzing timing reports.
• Proficient in using industry-standard EDA tools for DFT, timing, and simulation.
• Good knowledge of System Verilog.
• Experience with chiplet-based designs is a plus.

Education

Bachelor's degree in Electronics and Electrical Engineering, Computer Engineering, or a related field (equivalent or higher).

Application Process

If this role aligns with your career aspirations and you wish to be part of a dynamic and evolving company, we would greatly appreciate your application.

Apply online using the form below. Please note that only applications matching the job profile will be considered.

Join us at Kandou and help shape the future of technology!

Visit us at www.kandou.ai and follow us on LinkedIn.