DFT Lead / DFT Lead

Join Our Team as a DFT Lead in Lausanne, Switzerland

At Kandou, we thrive on challenges and embrace innovation. As a team of passionate and accomplished professionals, we are making a significant impact in the semiconductor industry. We are recognized as an innovative leader in high-speed, energy-efficient chip-to-chip link solutions that play a critical role in the evolution of the electronics industry. Our continuous development aims to meet the needs of today's customers and those of tomorrow. If you are eager to be part of a high-tech scale-up and are driven by pushing your limits and challenging the status quo, we have an exciting opportunity for you.

Role Overview

We are actively seeking a resourceful DFT Lead to join our team in Lausanne, Switzerland.

Key Responsibilities

• Lead DFT activities for next-generation products.
• Drive DFT architectures, methodologies, and tool flows for complex multi-million gate designs such as Analog/high bandwidth SerDes, DDR, and PCIe designs.
• Collaborate closely with the Physical Implementation team to define timing constraints in test modes and ensure successful tapeout.
• Possess a good understanding of ATE, with the ability to address probe and final test bring-up debug issues while leading the test engineering team for successful silicon bring-up and test program development.
• Define test plans by collaborating closely with teams and driving the development of functional/structural test patterns for the final/wafer test program.
• Work with teams to implement device qualification solutions for HTOL.
• Conduct lab bench silicon debugging to understand ATE bring-up issues.

Required Skills

• Excellent communication skills and a strong team player with a can-do attitude.
• Ability to mentor team members.
• Exceptional debugging skills.
• Good scripting skills for automation development.

Qualifications

• 12+ years of DFT experience, including architecture specification, implementation, test pattern development, and simulation.
• Proven track record of delivering DFT solutions for complex designs.
• Experience with IJTAG methodologies.
• Familiarity with hierarchical MBIST insertion, hierarchical scan insertion, and scan compression methodologies.
• Experience in ATPG pattern generation for various fault models, fault coverage analysis, and achieving high coverage metrics.
• Strong debugging capabilities for simulating patterns with timing.
• Experience in defining test mode constraints and analyzing timing reports.
• Familiarity with industry-standard EDA tools for DFT, timing, and simulation.
• Good knowledge of System Verilog.
• Experience with chiplet-based designs is a plus.

Education

Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering, or equivalent (or higher).

If this is the role you have been looking for and want to be part of a growing company with an exciting future, we genuinely want to hear from you. Apply online using the form below. Please note that only applications matching the job profile will be considered.

Together, We Kandou It!

For more information, visit us at www.kandou.ai and LinkedIn.