Analog Layout Engineer / Analog Layout Engineeress

Job Opportunity: Analog Layout Engineer (Lead)

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratize AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems—an essential barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution drastically reduces power consumption while maintaining high bandwidth and ultra-low latency, unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture represents not just an incremental improvement, but a foundational shift in how AI hardware is developed for the future.

Responsibilities

• Custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high-speed chip-to-chip communication links (SerDes up to and beyond 28Gb/s and/or memory I/O) in advanced semiconductor technology nodes.
• Layout and verification of very high-speed analog circuits.
• Close collaboration with the design team to understand requirements and implement effective solutions.
• Support IP and chip-level integration.
• Engagement with customers regarding requirements and IP delivery.
• Exposure to flip-chip package technologies.

Experience

• Proven experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits.
• Expertise in the layout of high-speed/frequency circuits such as amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, buffers, regulators, filters, data converters, etc.
• Understanding of layout approaches and techniques for high-speed circuits, including matching constraints, minimization of parasitics, power grids, and ESD requirements.
• Experience with modern semiconductor process technologies including 28nm, 14/16nm, and 7nm.
• Proficient in EDA tools for design and verification, such as Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modeling, EM, IR drop, and ESD.

Skills

• Self-motivated with a strong sense of ownership and responsibility.
• Excellent communicator and a collaborative team player.
• Ability to manage workload and schedules effectively while reporting to the internal management team.
• Background in Semiconductor Physics.

Education

Graduate in Electrical Engineering (E.E.)

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