Mixed Signal Verification Engineer / Mixed Signal Verification Engineeress

Kandou Bus SA - April 23, 2026

Join Our Team at Kandou

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratize AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution drastically reduces power consumption while preserving high bandwidth and ultra-low latency, unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture represents not just an incremental improvement, but a foundational shift in how AI hardware is built for the future.

Job Title: Mixed Signal Verification Engineer

Key Responsibilities:

  • Verification plan tasks in an analog/mixed signal environment related to high-speed SerDes designs.
  • Debug and flag issues in collaboration with the design team.
  • Enhance and develop new methodologies alongside the verification team and EDA vendors.
  • Document and track verification plan tasks, bug findings, and methodology work.

Skills:

  • Proficient scripting techniques.
  • Strong understanding of fabrication processes, process corners, simulations, and verification setups.
  • In-depth knowledge of electrical and discrete test benches/solvers, particularly regarding runtime optimization.
  • Familiarity with simulation tools and debugging techniques.
  • Understanding of revision control systems.
  • Excellent communication and reporting skills.

Experience:

  • At least 10 years of experience in digital/mixed signal/analog verification, including test bench design, module connections, and electrical/discrete partitioning.
  • Experience in behavioral modeling and basic knowledge of analog building blocks.
  • Proficient with simulators such as fast analog solvers (e.g., Cadence APS, SpectreX) and digital solvers (e.g., Cadence Xcelium).
  • Experience in constrained random testbench development.
  • Familiarity with System Verilog Assertions and Cadence Ocean Script.
  • Experience with Cadence Virtuoso Framework: Schematic editor, Assembler, AMS.
  • Experience in high-speed communication systems like SerDes is a plus.
  • A robust background in digital verification with some exposure to Specman/SV UVM and/or analog verification.

Education:

  • Graduated in Electrical Engineering.

If this role resonates with you and you wish to be part of a growing company with an exciting future, we would love to hear from you. Apply online using the form below. Please note that only applications matching the job profile will be considered.

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Learn More About Us

Visit us at www.kandou.ai and follow us on LinkedIn.

Location : St-Sulpice VD
Country : Switzerland

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