Mixed Signal Verification Engineer / Mixed Signal Verification Engineeress

Kandou Bus SA - April 16, 2026

Join Our Team at Kandou

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratize AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems—a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution significantly reduces power consumption while preserving high bandwidth and ultra-low latency—unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement; it’s a foundational shift in how AI hardware is built for the future.

Job Title: Mixed Signal Verification Engineer

Key Responsibilities:

  • Verification plan tasks in an analog/mixed signal environment related to high-speed SerDes designs
  • Debug and identify bugs in collaboration with the design team
  • Enhance and develop new methodologies with the verification team and EDA vendors
  • Document and track verification plan tasks, bug findings, and methodology work

Skills:

  • Proficient scripting techniques
  • Strong understanding of the fabrication process, process corners, simulation, and verification setup
  • Extensive knowledge of electrical and discrete test benches/solvers in terms of runtime optimization
  • In-depth knowledge of simulation tools and debugging techniques
  • Solid understanding of revision control
  • Excellent communication and reporting skills

Experience:

  • At least 10 years of experience in digital/mixed signal/analog verification, including test bench design, module connections, electrical/discrete partitioning, UDN, wreal, compile, and elaboration debug
  • Experience in behavioral modeling with a basic knowledge of analog building blocks
  • Familiarity with fast analog solvers (e.g., Cadence APS, SpectreX) and digital solvers (e.g., Cadence Xcelium)
  • Experience in constrained random testbench development
  • Knowledge of System Verilog Assertions
  • Experience with Cadence Ocean Script and Cadence Virtuoso Framework (Schematic editor, Assembler, AMS)
  • Background in high-speed communication systems such as SerDes is a plus
  • Good digital verification background with some Specman/SV UVM exposure and/or analog verification background

Education:

  • Graduated in Electrical Engineering

If this is the opportunity you have been looking for and you want to be part of a growing company with an exciting future, we would love to hear from you!

Apply online using the form below. Please note that only applications matching the job profile will be considered.

Visit us at www.kandou.ai and connect with us on LinkedIn.

Location : St-Sulpice VD
Country : Switzerland

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