Mixed Signal Verification Engineer / Mixed Signal Verification Engineeress

Kandou Bus SA - March 4, 2026

Join Our Team at Kandou!

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratize AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution significantly reduces power consumption while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement; it represents a foundational shift in how AI hardware is built for the future.

Job Title: Mixed Signal Verification Engineer

Key Responsibilities:

  • Implement verification plans in an analog/mixed signal environment related to high-speed SerDes designs.
  • Debug and address issues alongside the design team.
  • Enhance and develop new methodologies in collaboration with the verification team and EDA vendors.
  • Document and track verification tasks, bug findings, and methodology work.

Skills:

  • Proficient scripting techniques.
  • Strong understanding of the fabrication process, process corners, simulation, and verification setup.
  • Excellent knowledge of electrical and discrete test benches/solvers, particularly in terms of runtime optimization.
  • Thorough understanding of simulation tools and debugging techniques.
  • Good knowledge of revision control.
  • Strong communication and reporting skills.

Experience:

  • Minimum of 10 years of experience in digital/mixed signal/analog verification: test bench design, connecting modules, electrical/discrete partitioning, UDN, wreal, compile, and elaboration debug.
  • Experience in behavioral modeling and basic knowledge of analog building blocks.
  • Familiarity with simulators: fast analog solver (e.g., Cadence APS, SpectreX) and digital solver (e.g., Cadence Xcelium).
  • Background in constrained random test bench development.
  • Experience with System Verilog Assertions.
  • Proficiency in Cadence Ocean Script.
  • Familiarity with Cadence Virtuoso Framework: Schematic editor, Assembler, AMS.
  • Knowledge of high-speed communication systems such as SerDes is a plus.
  • Good digital verification background with some Specman/SV UVM exposure and/or analog verification experience.

Education:

  • Bachelor's degree in Electrical Engineering.

If this opportunity aligns with your aspirations and you want to be part of a growing company with an exciting future, we would love to hear from you. Together, We Kandou It!

Apply online using the form below. Please note that only applications matching the job profile will be considered.

Visit us at www.kandou.ai and follow us on LinkedIn.

Location : St-Sulpice VD
Country : Switzerland

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