Join Our Team at Kandou
At Kandou, we believe that challenges drive us and innovation is our calling. We are a team of passionate and accomplished professionals making a significant impact in the semiconductor industry. As a leader in high-speed and energy-efficient chip-to-chip link solutions, we are committed to evolving and meeting the demands of our customers today and in the future. If you're eager to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an exciting opportunity for you.
Position: Formal Verification Engineer
We are actively seeking a resourceful Formal Verification Engineer to join our team, with opportunities based in Lausanne, Switzerland, the UK (Reading/Northampton), Germany (Dortmund), or Denmark.
Key Responsibilities
- Develop formal verification methodologies and best practices.
- Participate in RTL design reviews.
- Prepare design verification plans based on design specifications.
- Document results and coverage metrics for formal sign-off.
- Plan and schedule assigned projects for timely completion.
- Maintain the design verification environment and track & close design bugs.
Skills
- Exceptional communication skills, with rigorous analytical thinking and strong teamwork capabilities.
- Proficient in scripting languages (Python, Perl, or TCL for automation), with experience in regression setup and management.
- Deep understanding of formal verification technologies.
- Strong knowledge of metrics-driven verification, including test planning and coverage closure.
- Proficiency in temporal logic assertion-based languages such as SVA or PSL.
- Familiarity with traditional simulation-based verification methodologies is a plus.
- Excellent analytical, problem-solving, and debugging skills.
- A strong grasp of instruction-set architectures, interrupt handling, and bus architectures.
- Knowledge of Cadence JasperGold and VManager is preferred.
Experience
- 5+ years of experience in the semiconductor industry.
- Proven track record in verifying complex designs, preferably in high-volume applications (FPGA or ASIC).
- Ability to balance quality with schedule constraints.
- Experience collaborating with RTL design engineers to develop formal micro-architecture specifications.
- Familiarity with SerDes and high-level protocols (e.g., PCIe, USB, DP) is advantageous.
- Delivered reusable and optimized formal models and verification codebases to enhance project efficiency.
Education
- Bachelor of Engineering in Electronics and Electrical Engineering (or equivalent higher qualification).
If this is the role you have been looking for and you want to be part of a growing company with an exciting future, then we would love to hear from you. Together, we Kandou It!
Apply online using the form below. Only applications matching the job profile will be considered.
Visit us at www.kandou.ai and follow us on LinkedIn.