Job Opportunity: Formal Verification Engineer
100% CDI immediately or as per agreement.
Challenges are our drive, and innovation is our calling. At Kandou, we are a team of passionate and accomplished professionals making a significant impact in the semiconductor industry. As an innovative leader in high-speed and energy-efficient chip-to-chip link solutions, we are committed to meeting the evolving demands of both today’s and tomorrow’s electronics industry. If you are eager to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an exciting opportunity for you!
Location
This position can be based in Lausanne, Switzerland, the UK (Reading/Northampton), Germany (Dortmund), or Denmark.
Key Responsibilities
- Develop formal verification methodologies and best practices.
- Participate in RTL design reviews.
- Prepare design verification plans based on design specifications.
- Document results and coverage metrics for formal sign-off.
- Plan and schedule assigned projects for timely completion.
- Maintain the design verification environment and track & close design bugs.
Skills
- Excellent communication skills and a rigorous analytical mindset with strong teamwork capabilities.
- Good scripting skills in Python, Perl, or TCL for automation, along with regression setup & management.
- Deep understanding of Formal Verification technologies.
- Strong knowledge of metrics-driven verification, including test planning and coverage closure.
- Proficiency in temporal logic assertion-based languages such as SVA or PSL.
- Familiarity with traditional simulation-based verification methodologies is a plus.
- Outstanding analytical, problem-solving, and debugging skills.
- Good understanding of instruction-set architectures, interrupt handling, and bus architectures.
- Knowledge of Cadence JasperGold and VManager is preferable.
Experience
- 5+ years of experience in the semiconductor industry.
- A proven track record in verifying complex designs, preferably in high-volume applications like FPGA or ASIC.
- Ability to manage trade-offs between quality and schedule.
- Experience working with RTL design engineers to develop a formal micro-architecture specification.
- Familiarity with SerDes and high-level protocols (e.g., PCIe, USB, DP) would be advantageous.
- Successfully delivered reusable and optimized formal models and verification codebases to enhance project efficiency.
Education
- Bachelor's degree in Electronics and Electrical Engineering (or equivalent/higher).
If this is the role you have been looking for and you want to be part of a growing company with an exciting future, we would love to hear from you. Together, We Kandou It!
Apply online using the form below. Please note that only applications matching the job profile will be considered.
Visit us at www.kandou.ai and our LinkedIn page.