Join Our Team at Kandou
At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratize AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution significantly reduces power consumption while maintaining high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Kandou's architecture represents not just an incremental improvement, but a foundational shift in how AI hardware is constructed for the future.
Position: Digital Verification Engineer
Key Responsibilities:
- Develop design verification methodologies and implement standard debug flows.
- Collaborate with designers in the verification and validation of circuit designs.
- Participate in design reviews.
- Prepare design verification plans based on design specifications.
- Plan and schedule assigned projects for timely completion.
- Utilize the latest techniques, tools, and technologies for design verification activities.
- Maintain the design verification environment and track & close design bugs.
Skills Required:
- Excellent communication skills, analytical mindset, and a strong team player.
- Proficient in scripting techniques, regression setup & management.
- Deep understanding of simulation and verification environments.
- Strong knowledge of metrics-driven verification (including test planning and coverage closure).
- Extensive experience with simulation tools and debugging techniques.
- Familiarity with verification planning and test bench development using the latest methodologies.
- Experience with third-party VIP usage and test development is a significant advantage.
- Experience with Assertion Based Verification is a plus.
Experience Required:
- 5+ years’ experience in the semiconductor industry.
- Proven track record in verifying complex designs (preferably in high-volume applications) - FPGA or ASIC.
- Skilled in navigating trade-offs between quality and schedule.
- Experience in constrained random test bench development.
- Familiarity with SerDes and high-level protocols (e.g., PCIe, USB, DP) is advantageous.
- Extensive digital verification background with some UVM experience.
Education:
Bachelor's degree in Electronics and Electrical Engineering (or equivalent higher qualification).
If this is the role you have been looking for and you want to be part of a growing company with an exciting future, then we would love to hear from you. Apply online using the form below.
Only applications matching the job profile will be considered.
Visit us at www.kandou.ai and our LinkedIn page.