Join Our Team at Kandou!
At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratize AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems—a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution dramatically reduces power consumption while preserving high bandwidth and ultra-low latency, unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture represents not just an incremental improvement but a foundational shift in how AI hardware is constructed for the future.
Job Title: Digital Verification Engineer
Key Responsibilities:
- Develop design verification methodologies and implement standard debug flows.
- Collaborate with designers for the verification and validation of circuit designs.
- Participate in design reviews.
- Prepare design verification plans based on design specifications.
- Plan and schedule assigned projects to ensure timely completion.
- Utilize the latest techniques, tools, and technologies for design verification activities.
- Maintain the design verification environment and track & close design bugs.
Skills:
- Excellent communication skills, with a rigorous analytical mindset and a strong team player attitude.
- Proficiency in scripting techniques, regression setup, and management.
- Deep understanding of simulation and verification environments.
- Strong knowledge of metrics-driven verification, including test planning and coverage closure.
- Extensive knowledge of simulation tools and debugging techniques.
- Understanding of verification planning and test bench development using the latest methodologies.
- Experience with 3rd party VIP usage and test development is a significant plus.
- Experience in Assertion Based Verification is an added advantage.
Experience:
- 5+ years of experience in the semiconductor industry.
- Proven track record in verifying complex designs, preferably in high-volume applications (FPGA or ASIC).
- Skilled in balancing quality with schedule constraints.
- Experience in constrained random test bench development.
- Familiarity with SerDes and high-level protocols (e.g., PCIe, USB, DP) is advantageous.
- Extensive digital verification background, with some UVM experience.
Education:
- Bachelor of Engineering in Electronics and Electrical Engineering (equivalent or higher).
If this is the role you have been looking for and you want to be part of a growing company with an exciting future, we would love to hear from you. Together, we Kandou it!
Apply online using the form below. Please note that only applications matching the job profile will be considered.
Visit us at www.kandou.ai and Kandou on LinkedIn.