DFT Lead Position in Lausanne, Switzerland
At Kandou, we believe that challenges drive innovation. We are a passionate team of professionals making significant advancements in the semiconductor industry. As leaders in high-speed and energy-efficient chip-chip link solutions, we are continuously evolving to meet the demands of today's and tomorrow's electronics markets. If you thrive in a high-tech environment and relish pushing your limits while challenging the status quo, we have the perfect opportunity for you.
Key Responsibilities
- Lead DFT activities for next-generation products.
- Drive DFT architectures, methodologies, and tool flows for complex multi-million gate designs, including Analog/high bandwidth SerDes, DDR, and PCIe designs.
- Collaborate closely with the physical implementation team to define timing constraints in test modes, aiding in convergence for successful tape-out.
- Possess a strong understanding of ATE, addressing probe and final test bring-up debug issues, and work with the test engineering team for successful silicon bring-up and test program development.
- Define comprehensive test plans by collaborating with various teams and drive the development of functional and structural tests for final/wafer test programs.
- Work closely with teams to establish device qualification solutions for HTOL.
- Lead laboratory silicon debug efforts to understand ATE bring-up issues.
Skills
- Exceptional communication skills and a strong team player with a proactive attitude.
- Ability to mentor team members effectively.
- Excellent debugging capabilities.
- Proficient scripting skills to aid in automation development.
Qualifications
- A minimum of 12 years of DFT experience, including architecture specification, implementation, test pattern development, and simulation.
- A proven track record of delivering effective DFT solutions for complex designs.
- Experience with IJTAG methodologies.
- Familiarity with hierarchical MBIST insertion, hierarchical scan insertion, and scan compression methodologies.
- Experience in ATPG pattern generation across various fault models, along with fault coverage analysis and achieving high coverage metrics.
- Strong debugging skills for simulating patterns with timing.
- Experience in defining test mode constraints and analyzing timing reports.
- Familiarity with industry-standard EDA tools for DFT, timing, and simulation.
- Solid knowledge of System Verilog.
- Experience with chiplet-based designs is a plus.
Education
- Bachelor's degree in Electronics and Electrical Engineering, Computer Engineering or an equivalent higher qualification.
If you are excited about this opportunity and wish to be a part of a growing company with an exhilarating future, we would love to hear from you! Apply online using the form below.
Note: Only applications matching the job profile will be considered.
Join us at www.kandou.ai and connect with us on LinkedIn.