DFT Lead Position at Kandou
At Kandou, challenges drive us and innovation calls us. We are a team of passionate professionals making waves in the semiconductor industry. As an innovative leader in high-speed and energy-efficient chip-to-chip link solutions, we are committed to evolving the electronics industry to meet the demands of both current and future customers. If you are eager to be part of a high-tech scale-up, motivated by pushing your limits, and ready to challenge the status quo, we have an exciting opportunity for you!
About the Role
We are actively seeking a resourceful DFT Lead based in Lausanne, Switzerland.
Key Responsibilities
- Lead DFT activity for next-generation products.
- Drive DFT architectures, methodologies, and tool flows for complex multi-million gate designs, including Analog/high bandwidth SerDes, DDR, and PCIe designs.
- Collaborate closely with the Physical Implementation team to define timing constraints in test modes, facilitating convergence for successful tape-out.
- Utilize knowledge of ATE to debug issues during probe and final test bring-up, ensuring successful Silicon integration and test program development.
- Define the test plan in collaboration with various teams and oversee the development of functional/structural tests for final and wafer test programs.
- Work with teams to establish device qualification solutions for HTOL.
- Lead lab bench silicon debugging to address ATE bring-up issues.
Skills
- Excellent communication skills and a strong team player with a positive, can-do attitude.
- Ability to mentor team members effectively.
- Outstanding debugging skills.
- Proficient scripting skills for automation development.
Qualifications
- 12+ years of DFT experience, including architecture specification, implementation, test pattern development, and simulation.
- Proven track record of delivering DFT solutions for complex designs.
- Experience with IJTAG methodologies.
- Familiarity with hierarchical MBIST insertion, hierarchical scan insertion, and scan compression methodologies.
- Experience in ATPG pattern generation for various fault models, fault coverage analysis, and optimizing for high coverage metrics.
- Strong debugging capabilities in simulating patterns with timing.
- Experience in defining test mode constraints and analyzing timing reports.
- Proficient with industry-standard EDA tools for DFT, timing, and simulation.
- Good knowledge of System Verilog.
- Experience with chiplet-based designs is a plus.
Education
- Bachelor's degree in Electronics and Electrical Engineering, Computer Engineering, or equivalent (or higher).
If this is the role you have been looking for and you want to be part of a growing company with an exciting future, we would love to hear from you. Apply online using the form below. Please note that only applications matching the job profile will be considered.
Together, We Kandou It!
Visit us at www.kandou.ai and LinkedIn.